Efficient Optimization Of FPGA on-Chip Memory for Image Processing Algorithm

Abstract

This paper is concerned with efficient optimization and low power implementation of FPGA on-chip memories in image processing algorithms. In recent years on chip memories are expected to increase continuously which depends upon the application for future generation portable devices and high performance processors. Memory plays a major role in image processing applications more than 90% of the consumed power in the system is by the memory part. This paper provides a novel approach by making SPSRAM to function like a DPSRAM. It supports most of the access schemes for Image processing algorithms and also when the readout changes the memories need not to be redesigned. It achieves high throughput, less hardware requirement and high bandwidth utilization. The full bandwidth utilization has been achieved by splitting the on-chip memory into four sub banks. The Optimization of power can be done by making any two banks active at a time.It is well suited for various image coding algorithms when compared to the typical SPSRAM and TDP SRAM.It finds applications in most of the parallel processing fields. GENERAL TERMS Design, measurement, performance, theory.