The optimization of low power operation SRAM circuit for 32nm node

Abstract

As CMOS technology is advanced in recent years, the operation of SRAM becomes critical issue for further scaling. It is crucial for realizing the SRAM to keep static noise margin (SNM) and write margin (WM) large enough to get stability and overcome random dopant and process fluctuations. Also, suppression of leakage current is another key issue. The major sources of leakage current are the gate direct tunneling current, the sub-threshold leakage and the reverse biased band-to-band-tunneling junction leakage. To reduce total chip power, these leakage components must be suppressed. In this paper, we have focused on the optimization of low power operation SRAM circuit for 32 nm node with TCAD optimizing the relationship among margin, leakage current and access time. To conduct the circuit design principle, we define the new quality factor and evaluate the 32nm SRAM performance with this defined formula.