Performance analysis of conventional SRAM with higher order SRAM topologies

Abstract

The growth in digital consumer electronics has evoked a tremendous rise in performance of portable devices. To meet these demands, there is a need of primary memory and thus Static Random Access Memory (SRAM) serves this purpose. Technical innovations have provided the improved memory density and speed. Innovations in memory technology are reflected in terms of high-density, high-speed and low-power memory cells. Therefore, low power, high speed and high stability are the major concerns in designing SRAM cells. Scaling down the voltage meets the low-power requirements of the cell but at the same time delay increases and the stability degrades. Thus, there is always a trade-off between the performance parameters. On the basis of particular application, various methods like the sizing of device, scaling of voltage and architectural techniques are used to improve the overall performance of memory cells. This paper compares different architectural designs of SRAM topologies, such as 6T, 7T, 8T and 9T, on the basis of stability (write SNM, read SNM and hold SNM), power consumption and delay. For example, feedback loop cutting architectural technique in 7T SRAM cell increases the write stability as compared to 6T SRAM cell but at the same time area increases. An attempt has been made to identify topologies with optimized overall performance.