RTOS Solution for NoC-Based COTS MPSoC Usage in Mixed-Criticality Systems

Abstract

Multi-core system on chip (MPSoC) is a clear trend for the future embedded systems. Network-on-chip (NoC) is the most scalable interconnection, allowing to have hundreds of cores on the same chip. On the other hand, safety critical applications (e.g., avionic) require the system to present a set of strict guarantees, which are difficult to achieve for MPSoC-based systems. In this work we target Commercial Off-The-Shelf (COTS) NoC-based MPSoC for the mixed criticality systems, in the safety critical field. The focus of the proposed work is on the issue of contention on the NoC and the related temporal interference. As the main contribution, we propose a partitioning technique to enable the usage of COTS NoC-based MPSoC for the mixed criticality systems, enabling an unbounded number of levels of criticality to be deployed. The proposed technique exploits the deterministic routing algorithm of the NoC and it is suitable for any NoC-based MPSoC which meets a set of fairly common characteristics. The partitioning technique is intended to have a purely software implementation as a module of a real-time operating system, which will allow easier certification as well. The proposed approach overcomes the concept of strict network partitioning between regions, as it implements traffic isolation allowing partitions to overlap. As a further contribution this paper describes the cost of proposed solution in terms of the network connectivity reduction. A set of rules to enable an efficient usage of the proposed solution has been provided.