Prototyping for the concurrent development of an IEEE 802.11 wireless LAN chipset

Abstract

This paper describes how an FPGA based prototype environment aided the development of two multi-million gate ASICs: an IEBE 802.11 medium access controller and an IEEE 802.11a/b/g physical layer processor. Prototyping the ASICs on a reconfigurable platform enabled concurrent development by the hardware and software teams, and provided a high degree of confidence in the designs. The capabilities of modern FPGAs and their development tools allowed us to easily and quickly retarget the complex ASICs into FPGAs, enabling us to integrate the prototyping effort into our design flow from the start of the project. The effect was to accelerate the development cycle and generate an ASIC which had been through one pass of beta testing before tape-out. © Springer-Verlag Berlin Heidelberg 2003.