From process variations to reliability: A survey of timing of digital circuits in the nanometer era

11Citations
Citations of this article
9Readers
Mendeley users who have this article in their library.

Abstract

In advanced technology nodes, transistors and interconnects with shrinking physical dimensions suffer large process variations during manufacturing and are prone to reliability issues. These underlying changes require an overhaul of the design methodologies for digital circuits. In this paper, we provide an overview of techniques introduced recently to analyze the effect of uncertainty in manufacturing and reliability issues of devices due to the diminishing feature size. These techniques range from variation/aging modeling to circuit-level analysis. In addition, active techniques to counter these effects, such as clock skew tuning and voltage tuning are also covered in this paper.

Cite

CITATION STYLE

APA

Li, B., Hashimoto, M., & Schlichtmann, U. (2018). From process variations to reliability: A survey of timing of digital circuits in the nanometer era. IPSJ Transactions on System LSI Design Methodology, 11, 2–15. https://doi.org/10.2197/ipsjtsldm.11.2

Register to see more suggestions

Mendeley helps you to discover research relevant for your work.

Already have an account?

Save time finding and organizing research with Mendeley

Sign up for free