Process corner analysis for folding and interpolating ADC

Abstract

Folding and Interpolating ADC have been shown to be an effective means of digitization of high bandwidth signals at intermediate resolution. The paper designs Folding and Interpolating ADC using cascaded folding amplifier to observe the effect of process variations. The primary circuit effects, resulted from process variations that are liable to degrade the performance of ADC are transistor mismatch, resistor mismatch and amplifier-comparator offsets. The device matching in reference generation, folding amplifier, interpolation and comparator offsets specify overall performance of ADC. Since the mismatches are random, Monte Carlo Analysis is used to estimate the linearity performance. In this paper the design is simulated using 0.35 μm, 3.3V to study the effect of process corners. © 2011 Springer-Verlag.