A novel memory subsystem and computational model for parallel reconfigurable architectures

Abstract

While FPGA and other reconfigurable technologies have dramatically increased in size and speed, memory technology has had only modest improvements. Relative to logic speeds, memory latency is virtually flat and physical constraints on external pins limit memory bandwidth. Unfortunately, the traditional cache hierarchy found in fixedfunction integrated circuits has evolved to support sequential processors and is ineffective for highly parallel architectures. This paper proposes a novel memory subsystem and computational model for reconfigurable architectures. It envisions a system where computational cores are oversubscribed with atomic tasks and the memory subsystem enables (1) hiding of latency by enabling the cores to overlap computation and memory transactions and (2) the system to fully utilize the available memory bandwidth. The first step in this grand vision is to change the memory model. Instead of a byte-Addressable, global address space, a named segment memory controller is introduced and an FPGA-based implementation presented in this paper. © 2014 Springer-Verlag Berlin Heidelberg.