Reconfiguration graph grammar for massively parallel, fault tolerant computers

Abstract

Reconfiguration for fault tolerance is the process of excluding faulty processors from an array of interconnected processors and including spare processors to take their place. Reconfiguration Graph Grammar (RGG) is introduced as a model supporting the design and analysis of these Reconfiguration algorithms. A formal description is given, as well as several theorems, with proofs, concerning the properties of RGG that make it well suited for modeling Reconfiguration. An example RGG-based Reconfiguration algorithm is described and demonstrated.