Differential power analysis of AES ASIC implementations with various S-box circuits

Abstract

Differential Power Analysis experiments are conducted on various ASIC implementations of AES with different S-box architectures: (i) an inverter over Galois Field GF(((22)2)2), (ii) table, (iii) PPRM (Positive Polarity Reed-Muller forms), and (iv) 3-stage PPRM. Dedicated ASIC is developed and its power is measured on the standard evaluation board SASEBO-R. The results show that the S-box implementations have a significant impact on DPA resistance. The results are also compared with that of FPGA implementations to investigate the difference between the platforms. ©2009 IEEE.