Differential power analysis of AES ASIC implementations with various S-box circuits

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Abstract

Differential Power Analysis experiments are conducted on various ASIC implementations of AES with different S-box architectures: (i) an inverter over Galois Field GF(((22)2)2), (ii) table, (iii) PPRM (Positive Polarity Reed-Muller forms), and (iv) 3-stage PPRM. Dedicated ASIC is developed and its power is measured on the standard evaluation board SASEBO-R. The results show that the S-box implementations have a significant impact on DPA resistance. The results are also compared with that of FPGA implementations to investigate the difference between the platforms.

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Sugawara, T., Homma, N., Aoki, T., & Satoh, A. (2009). Differential power analysis of AES ASIC implementations with various S-box circuits. In ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program (pp. 395–398). https://doi.org/10.1109/ECCTD.2009.5275004

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