Design of High Performance ALU Using Vedic Mathematics

Abstract

This article proposes a Vedic multiplier-based design of multiply and accumulate unit by employing UrdhvaTiryagbhyam Sutra. Further, it implements an efficacious ALU with 32-bit architecture. Simulation analysis disclosed the comparison of proposed 32-bit ALU with existing architectures. In addition, complexity in hardware, area and delay reduction demonstrated that proposed 32-bit ALU is more efficient over conventional architectures.