Automatic interface generation between incompatible Intellectual Properties (IPs) from UML models

Abstract

This paper presents an UML based tool for incompatible hardware Intellectual properties (IPs) integration. Our aim is to provide Systems On Chips (SOCs) designers with a UML based environment for modeling incompatible IPs, automatic generation of interface between IPs, and functional simulation. In our case, each IP is modeled as an UML component with a well defined interface including input and output signals and some attributes. The whole SOC is modeled via UML structure diagram. Memory timing constraints are modeled via UML timing diagrams. Communication protocols for incompatible IPs are modeled via UML Statecharts with hierarchic and concurrent states. From these diagrams, a Finite State Machine with Data path (FSMD) for interface is generated automatically. Functional simulation of the interface is performed by translating the result FSMD to a VHDL code. © 2011 Springer-Verlag.