Area/performance improvement of NoC architectures

Abstract

The design of electronic systems in a System-on-Chip (SoC) depends on the reliable and efficient interconnection of many different components. The Network-on-Chip (NoC) has emerged as a scalable communication infrastructure with high bandwidth able to tackle the communication needs of future SoC. In this paper, we present a generic NoC architecture that can be customized to the specific communication needs of an application in order to reduce the area with minimal degradation of the latency of the system. © Springer-Verlag Berlin Heidelberg 2006.