An Efficient Implementation of an Effective PFD-CP for Low Power Low-Jitter CP-PLL

Abstract

A new efficient Phase-frequency Detector (PFD) paired with a new Charge-Pump (CP) is presented in this paper. This PFD-CP topology uses minimum sized devices of optimal minimum energy. The proposed PFD uses two pre-charged logic stages followed by static CMOS inverters without reset path cell or additional delay cells which leads to having a minimum blind zone, removing dead zone and occupying small chip area. Besides, the proposed design topology allows lowering power dissipation and improving speed, and can be used in high-speed CP-PLL applied in RF communication systems. Also, the paper presents an effective CP design for low-power and wide Voltage Controlled Oscillator (VCO) control voltage swing, that solely uses two CMOS inverters for charging and discharging processes, and therefore can form an effective PFD-CP topology suitable for applications where performance is needed, meanwhile minimizing energy consumption is key. Simulation results of the implemented circuit are discussed accordingly.