Selective attention in multi-chip address-event systems

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Abstract

Selective attention is the strategy used by biological systems to cope with the inherent limits in their available computational resources, in order to efficiently process sensory information. The same strategy can be used in artificial systems that have to process vast amounts of sensory data with limited resources. In this paper we present a neuromorphic VLSI device, the "Selective Attention Chip" (SAC), which can be used to implement these models in multi-chip address-event systems. We also describe a real-time sensory-motor system, which integrates the SAC with a dynamic vision sensor and a robotic actuator. We present experimental results from each component in the system, and demonstrate how the complete system implements a real-time stimulus-driven selective attention model. © 2009 by the authors.

Figures

  • Figure 1. Block diagram of the SAC pixel. Each pixel receives sequences of spikes from the AER bus and competes for saliency by means of lateral connections. The winning pixel sends its address to the AER bus and self-inhibits via the inhibitory synapse.
  • Figure 2. Input excitatory synapse: (a) Circuit diagram of the excitatory synapse, comprising the DPI circuit and the STD circuit. (b) Mean and standard deviation (shaded areas) of the input current of the WTA cell versus the input frequency, when the DPI is stimulated with a spike train of constant frequency at 100 Hz, for different time constant and weight settings and disabled STD.
  • Figure 3. Current-mode hysteretic WTA circuit with diode-source degeneration “DS”, local excitation “EXC”, local inhibition “INH” and positive feedback “HYST”.
  • Figure 4. Hysteresis measured by observing the output activity of the I&F neuron: (a) Instantaneous input frequency of the spike train sent to pixel 1, and to pixel 2. (b) Center of mass of the chip’s activity versus the input frequency of pixel 2 for different amplitudes of the hysteretic current.
  • Figure 5. Lateral excitation. Spatial impulse response of the WTA resistive grid (see ”EXC” in Figure 3). The difference between the response for Vexc > 0 and the response for Vexc = Gnd is plotted. (a) Example of the spatial response for Vexc = 200 mV, (b) Cross section with mean and standard deviation of the data recorded from the pixels belonging to the same row and column as the central pixel, for different values of the bias Vexc.
  • Figure 6. Functional role of lateral excitation. (a) Center of mass of the activity of the array, when stimulating a single pixel with a constant frequency and a blob, for different values of the bias Vexc. The activity of all of the pixels belonging to the blob is added together, and represented as a single pixel. (b) Center of mass of the chip activity, when two blobs are stimulated. (c) Baseline activity without hysteresis, when either single pixels or blobs are stimulated.
  • Figure 7. I&F circuit diagram. It comprises a membrane capacitor, a constant leak “LK”, a spike generating circuit “SPK” with a positive feedback “Na” mimicking the fast activation of sodium channels and a reset and hyperpolarizing circuit that mimics the activation of late potassium channels “K”. The “ADAP” circuit implements spike frequency adaptation by calcium accumulation.
  • Figure 8. Inhibition of return: typical traces of the internal variables Vnet (top trace), Vmem (bottom trace), and Vior (black middle trace), recorded from one test pixel, for three combinations of inhibition weight (Vwinh) and time constant (Vτinh). (a) Vwinh = 2.42 V, Vτinh = 10 mV, (b) Vwinh = 2.58 V, Vτinh = 30 mV,(c) Vwinh = 2.44 V, Vτinh = 80 mV.

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CITATION STYLE

APA

Bartolozzi, C., & Indiveri, G. (2009). Selective attention in multi-chip address-event systems. Sensors, 9(7), 5076–5098. https://doi.org/10.3390/s90705076

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