Advancements and Challenges on Parasitic Extraction for Advanced Process Technologies

Abstract

As the feature size scales down, the process technology becomes more complicated and the design margin shrinks, accurate parasitic extraction during IC design is largely demanded. In this invited paper, we survey the recent advancements on parasitic extraction techniques, especially those enhancing the floating random walk based capacitance solver and incorporating machine learning methods. The work dealing with process variation are also addressed. After that, we briefly discuss the challenges for capacitance extraction under advanced process technologies, including manufactureaware geometry variations and middle-end-of-line (MEOL) parasitic extraction, etc.