ASIC implementation of low power, area efficient adaptive FIR filter using pipelined DA

Abstract

This paper presents a brief information on the ASIC implementation of adaptive finite impulse response (FIR) filters based on pipelined distributed arithmetic (DA) architecture. The pipelined sum of partial products of input samples is stored in the lookup table of the DA. The area of the proposed design is reduced by replacing the adder of the shift accumulation unit with the carry-save adder. The throughput rate of the design is increased by having fast clock to the carry-save adder and slow clock to the remaining circuit. The proposed design is implemented in Synopsys 90 nm CMOS technology. The area delay product (ADP), minimum cycle period (MCP), and energy per sample are reduced when compared with the conventional DA-based architectures.