Design of low power montgomery multiplier using clock technique

Abstract

Looking at the current scenario, digital systems are more beneficial than the analog system. The power consumption and speed are the major performance criteria for any digital system. It is very important to have a high speed and less power consumption in all devices. The priority of having a high speed or less power consumption depends on the need of the system. This paper presents the implementation of high-performance Montgomery modular multiplier which is also low power consuming. It works upon a simple and efficient Montgomery multiplication algorithm. Hardware as well as software fields find applications of Montgomery modular multiplication. Hardware implementations use direct data path, making them faster in contrast to software implementations. Some real-time applications of software implementations are not fast enough; the reason being their flexibility. Such kind of implementations hasve an additive advantage that they are capable of being customized as per new algorithms. The power consumption of the proposed design is 14mW and has been improved by 59.1% from the existing design.