Abstract
In this paper, we characterized the TPC-H benchmark on an Itanium II processor. Our experiment results clearly demonstrate: (1) On Itanium II processor, the memory stall time is dominanted by first level (Ll) instruction cache and third level (L3) data cache misses; (2) Index can reduces L3 data cache misses dramatically but increases a slightly more Condition Branch Instruction misprediction (BMP) rate. These revealed characteristics are expected to benefit database performance optimizations and database architecture design on next-generation processors. © Springer-Verlag Berlin Heidelberg 2007.
Cite
CITATION STYLE
Liu, D., Wang, S., Qin, B., & Gong, W. (2007). Characterizing DSS workloads from the processor perspective. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4537 LNCS, pp. 235–240). Springer Verlag. https://doi.org/10.1007/978-3-540-72909-9_26
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