An effective reconfiguration process for fault-tolerant VLSI/WSI array processors

Abstract

Most of previous literatures predict the yield of fault-tolerant VLSI/WSI arrays first adopting the fault-free switching network, only considering the step of reconfiguration algorithm, and assuming that the steps of placement, routing and switch programming are all perfect. Consequently, this simplified yield estimation model may give quite misleading results. The main work of this paper is to propose an effective reconfiguration process which comprises the reconfiguration, placement, routing and switch programming algorithms and develop a thorough yield simulation tool for the proposed reconfiguration process and redundancy schemes. To be accurate, in our yield simulation, we take both the PE and switch failures into account. Therefore, our yield prediction model will provide more precise and meaningful data. This yield simulation tool can also offer the information of the performance degradation probability distribution, reconfiguration, placement, routing and switch programming algorithm survival probability. The yield simulation is performed to validate our redundancy schemes.