A comprehensive investigation of formal system verification tools and approaches

Abstract

System testing is a complex process that takes major portion of total project cost. The verification of the system is usually performed once major implementation is carried out in the desired programming language. It is more costly and time consuming to fix the errors reported after implementation. In this context, formal verification is used to mathematically test the system in early development stages. Although there are several formalisms and tools available to perform formal verification, it is always difficult to choose the right formalism and tool for the system verification. Therefore, in this article, a comprehensive investigation of modern formal techniques and tools is performed. Particularly, 30 research studies published since 2009–2017 are selected where formal approaches and tools have been utilized for system verification (hardware as well as software systems). This leads to identify 3 formal system verification approaches, 6 formalisms and 12 formal verification tools. Finally, a detailed comparison of leading formal verification tools is performed.