Performance evaluation of vedic multiplier using multiplexer-based adders

Abstract

Faster multipliers are the necessary elements in most of the applications such as the Internet of Things (IoT), Image, and Digital Signal Processing applications. In the present scenario, Vedic multiplier using Urdhva-Tiryagbyam is preeminent in the performance evaluation of parameters such as area, power, and delay. By observing the architecture of conventional Vedic multiplier, it is evident that performance is still improvised by using modified half adders and full adders. Vedic multiplier using modified adders is coded in Verilog HDL and to convey the simulation and synthesis, XILINX ISE 12.2 software is used on Spartan 3E kit. In addition, the proposed multipliers are compared with the Conventional Vedic multiplier in terms of slices, LUTs, and combinational delay.