A scalable architecture for montgomery multiplication

Abstract

This paper describes the methodology and design of a scala ble Montgomery multiplication module. There is no limitation on the maximum number of bits manipulated by the multiplier, and the sel ection of the word-size is made according to the available area and/or desired performance. We describe the general view of the new architec ture, analyze hardware organization for its parallel computation, and discuss design tradeoffs which are useful to identify the best hardware configuration.