A review of research on network-on-chip simulator

Abstract

The huge design space of Network-on-Chip raise the need of simulators for NoC to efficiently evaluate the performance and select the optimal architecture. This paper presents a review of research on NoC simulators, differentiates the current approaches into three categories: regular network simulators, dedicated NoC simulators, and full-system simulators. We compares the current NoC simulators according to topologies, routing and switching algorithms, traffic models, and discuss the open issues and developing trends in this field. © 2011 Springer-Verlag Berlin Heidelberg.