A coarse grain parallel architecture for functional languages

Abstract

Design considerations of a coarse grain parallel architecture for functional languages are presented. These include extensibility, the separation of computation and control of parallelism, the introduction of partially shared memories, a cluster concept and a conceptually centralised loadbalancing mechanism. The implementation of parallel reduction is based on annotation of coarse grain strict arguments. Speed-up figures for a number of application programs are obtained by measurements on a pilot implementation of the architecture. The experience obtained with the experimental machine suggests the use of VLSI for specialised parts of the implementation. The proposed design is compared with related architectures.