In this chapter, we look at modeling sequential logic using the more sophisticated behavioral modeling techniques presented in Chap. 8. We begin by looking at modeling sequential storage devices. Next, we look at the behavioral modeling of finite-state machines. Finally, we look at register transfer level, or RTL modeling. The goal of this chapter is to provide an understanding of how hardware description languages can be used to create behavioral models of synchronous digital systems
CITATION STYLE
LaMeres, B. J. (2017). Behavioral Modeling of Sequential Logic. In Introduction to Logic Circuits & Logic Design with VHDL (pp. 309–340). Springer International Publishing. https://doi.org/10.1007/978-3-319-34195-8_9
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