On-the-fly architecture design and implementation of a real-time stereovision system

Abstract

Stereovision is a way to reconstruct 3D information that is inspired from the basic mechanism of human eyes. When dealing with real-time stereo computation, the use of specialized hardware architecture becomes mandatory. Consequently, many research work dealt with the implementation of this process using FPGA platforms, each one with a particular emphasis. This paper describes a novel architecture that optimizes the memory size to be used in a pipelined, pixel clock synchronized, stereo vision system. Consequently, this last provides the disparity map in real-time. The resulting work is a tiny architecture capable of processing stereo video streams on-the-fly, without external memory storage for stereo pairs. This implementation is fully pipelined and covers the entire stereovision process. In addition, the hardware implementation of the Hamming distance as well as the index computation were enhanced. The design is generic as the disparity window, the image size, and the matching algorithm can be selected (Census or SAD). The hardware implementation shows better performance over previous studies.