Massively simulating adiabatic bifurcations with FPGA to solve combinatorial optimization

Abstract

Combinatorial optimizations are widely adopted in scientific and engineering applications, such as VLSI design, automated machine learning (AutoML), and compiler design. Combinatorial optimization problems are notoriously challenging to exactly solve due to the NP-hardness. Scientists have long discovered that numerically simulating classical nonlinear Hamiltonian systems can effectively solve manywell-known combinatorial optimization problems. However, such physical simulation typically requires a massive amount of computation, which even outstrips the logic capability of modern reconfigurable digital fabrics. In this work, we proposed an FPGA-based general combinatorial optimization problem solver which achieved ultra-high performance and scalability. Specifically, we first reformulated a broad range of combinatorial optimization problems with a general graph-based data structure called the Ising model. Second, instead of utilizing classical simulated annealing to find an approximate solution, we utilized a new heuristic algorithm, simulated bifurcation, to search for solutions. Third, we designed an efficient hardware architecture to fully exploit FPGAs' potentials to accelerate the algorithm, and proposed three hardware-software cooptimizations to further improve the performance. By experimenting on benchmarks, our proposal outperformed the state-of-the-art simulated annealing optimization solver by up to 10.91 times.