The configuration ratio: A model for simulating CMOS intra-gate bridge with variable logic thresholds

Abstract

In order to simulate the effects of a bridging fault it is necessary to accurately determine the intermediate voltage of the shortednodes, deduce the intermediate voltage of the faulty gate output and compare it to the logic threshold voltage of the driven gates. This paper presents a general model called “the Configuration Ratio model” which can be used to determine if a particular structure of transistors gives an intermediate voltage which is higher orlowerthan a given threshold vottage. The approach is extremelyfasterthan the previous ones since no SPICE simulation is required. The accuracy is of O.O6V to compare with SPICE simulations. In case of library based design a preliminary library characterization is possible allowing a very fast time during fault simulation.