VHDL Simulation-Based Fault Injection Techniques

Abstract

This chapter presents an overview of some principal VHDL simulation-based fault injection techniques. Significant designs and tools, as well as their advantages and drawbacks, are shown. Also, VFIT, a VHDL simulation-based fault injection tool developed by the GSTF (Fault Tolerant Systems Group — Polytechnic University of Valencia) to run on a PC platform, is described. Finally, an example of application of VFIT to validate the dependability of a fault-tolerant microcomputer system is shown. We have studied the pathology of the propagated errors, measured their latencies, and calculated both detection and recovery coverages.