Performance Analysis of 8-Bit Vedic Multipliers Using HDL Programming

Abstract

Now a days, Multiplier plays a vital role in the implementation of various digital and signal processing applications. As the technology is advancing at a good pace, most of the designers opted for a multiplier with various design objectives like low power dissipation, high speed, less area or a combination of them. In this work, architectures of various conventional multipliers and Vedic multiplier based on UT and Nikhalam Sutra are studied and implemented. The simulation results of theses multipliers are plotted. A comparison table of various multipliers is tabulated in terms of area and delay.