Compact Modeling of Carbon Nanotube Transistor and Interconnects

Abstract

Silicon based devices have dominated mainstream computing for the last four decades. Achieving sustainable scaling of physical dimensions and device performance (Moore, 1965) has been key to their success. However, due to limitations in fundamental physics, materials, and manufacturing limits, this scaling trend has slowed down. Examples of major bottlenecks for continual scaling include short channel effects, high leakage currents(Wann et al., October 1996), excessive process variations(Bowman et al., 2002) and reliability issues(Chen et al., February 1985). These pitfalls are posing dramatic challenges to fabrication of circuits with scaled silicon devices. As we approach these fundamental limits in planar CMOS process , it becomes imperative to search for alternative materials, structures, devices as well as design paradigm to replace silicon transistor as the building block of future nanoelectronics. Novel structures like FinFETs(Hisamoto et al., 2000) and Trigate devices(Doyle et al., 2003), strained channel to enhance carrier mobility(Welser et al., 1994) and high-K/metal gate to reduce gate leakage current(Chau et al., 2004) have been proposed. These innovations have limited potential and will extend the scaling by a generation or two. Amongst more radical search for new devices and materials, carbon nanotube electronics has attracted significant attention owing to their high intrinsic carrier mobility. For the sake of simplicity, carbon nanotubes can be defined as hollow cylinders made up of one (single-walled) or more (multi-walled) concentric layer of carbon atoms arranged in a hexagonal lattice structure, which is similar to a rolled-up sheet of graphene. With diameters of 1-4 nm and the length extending to several micrometers, carbon nanotube is essentially a one dimensional object possessing unique properties attributed to low dimensional structures , such as 1-D density of state for carriers (McEuen et al., 2002). This enables reduced phase space for scattering and near ballistic transport of carriers when the device dimension is less than the mean-free path for scattering. Depending on the direction in which the graphene sheet is rolled up, single-walled carbon nanotubes is either metallic or semicon-ducting. Hence CNT transistor and interconnect can be made out of semiconducting and metallic nanotubes, respectively. Functional field effect transistors with semiconducting carbon nanotube channel(Lin et al., 2005; Zhang et al., 2006) and metallic nanotubes as intercon-nects(Close & Wong, 2007) have been demonstrated. Theoretically, it is possible to get current densities much higher than that of silicon devices with a similar dimension(Raychowdhury et al., 2006) using multiple CNTs in parallel. To speed up the evolution of this novel alternative technology, parallel efforts in circuit design are essential. For this purpose, the development of compact model is a vitally important 12 www.intechopen.com