Effective network interface architecture for fault-tolerant mechanism network-on-chip

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Basically, the denser integration capabilities will enable silicon technology scaling continuously. But in silicon technology higher variability and susceptibility will obtain. In this paper an effective network interfaces architecture if introduced for fault tolerant mechanism network on chip. A chip multi processor is introduced on chip components but this processor will not give effective output. Hence, the introduced system gives high throughput in modern network on chips. This system will exploit the speed of appropriate wire engineering which will transfer the long distance in single clock cycle. The data will be transferred between NOC routers by using Network interface (NI) and IP cores. Hence the proposed architecture will save the life time and overcome the issues of previous system.




Radha, K., Ramakrishna, K., & Guduru, K. (2019). Effective network interface architecture for fault-tolerant mechanism network-on-chip. International Journal of Innovative Technology and Exploring Engineering, 8(12), 1454–1458. https://doi.org/10.35940/ijitee.L3949.1081219

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