A fair thread-aware memory scheduling algorithm for chip multiprocessor

Abstract

In Chip multiprocessor (CMP) systems, DRAM memory is a critical resource shared among cores. Scheduled by one single memory controller, memory access requests from different cores may interfere with each other. This interference causes extra waiting time for threads and leads to negligible overall system performance loss. In conventional thread-unaware memory scheduling patterns, different threads probably experience extremely different performance; one thread is starving severely while another is continuously served. Therefore, fairness should also be considered besides data throughput in CMP memory access scheduling to maintain the overall system performance. This paper proposes a Fair Thread-Aware Memory scheduling algorithm (FTAM) that ensures both the fairness and memory system performance. FTAM algorithm schedules requests from different threads by considering multiple factors, including the source thread information, the arriving time and the serving history of each thread. As such FTAM considers the memory characteristic of each thread while maintains a good fairness among threads to avoid performance loss. Simulation shows that FTAM significantly improves the system fairness by decreasing the unfairness index from 0.39 to 0.08 without sacrificing data throughput compared with conventional scheduling algorithm. © Springer-Verlag Berlin Heidelberg 2010.