A hardware architecture for calculating LBP-based image region descriptors

Abstract

In this paper, an efficient hardware architecture, enabling the computation of LBP-based image region descriptors is presented. The complete region descriptor is formed by combining individual local descriptors and arranging them into a grid, as typically used in object detection and recognition. The proposed solution performs massively parallel, pipelined computations, facilitating the processing of over two hundred VGA frames per second, and can easily be adopted to different window and grid sizes for the use of other descriptors.