Optimization of digital audio processing algorithms suitable for hearing aids

Abstract

In the current embedded systems market the hearing aid technology is one very special target. These very small devices suffer -more than usual mobile devices - on the one hand from insufficient power supplies and thus very limited operating times. On the other hand the need for improved signal processing is obvious: noise reduction, speech intelligibility, auditory scene analysis are promising enhancements for these devices to enable the hearing impaired user a more comfortable and normal life. These facts make the design gap seen in normal embedded systems design even worse. Therefore early power estimation and optimization become more important. Nowadays hearing aids are often based on specially optimized DSPs and ?Ps primarily for commercial reasons like time-to-market, the ability of last minute changes and during lifetime adaptations of software to new research results or market demands. However, a number of computation intensive functions need to be performed by almost any digital hearing aid, e.g. Fourier Transforms, band pass filters, Inverse Fourier Transform. These can be realized much more power efficiently by dedicated HW-coprocessors, which may be parameterized. Hence Low Power design for hearing aids includes: algorithm design and optimization, HW-/SW-partitioning, processor selection, SW-optimization and co-processor design and optimization. To meet this need, power estimation even on the algorithmic level has become an important step in the design flow. This helps the designer to choose the right algorithm right from the start and much optimisation potential can be used due to the focus on the crucial parts. Here we focus on the co-processor design and power optimization. The power consumption of a co-processor is primarily determined by the dynamic switching power during calculations and the static leakage power. An estimation of both contributors requires analyzing the architecture and its activity during the expected operation of the device. In early stages of the design neither information is available yet. A new analysis and optimization tool has been developed to generate this information from an executable specification and a typical application scenario. The tool ORINOCO, which was developed at the OFFIS research institute and now is being commercialized by ChipVision Design Systems, analyzes a design specification given in C or SystemC and automatically generates the necessary information of a power optimized architecture implementing that specification and the activity within that architecture. It further includes power macro models of the components of that architecture which allow making an estimate of the to-be-expected static and dynamic power consumption of a co-processor. It thus enables power optimization in the earliest and thus most efficient and effective phases of a design. The talk gives an overview of the actual approach of designing hardware implementations of digital audio signal processing algorithms under strong power constraints. The main focus of the talk is on the analysis and optimization of algorithms in the early stage of design and on the modelling of components needed for high-level power estimation. The different optimization steps will be illustrated by a coprocessor design of a hearing aid. © Springer-Verlag Berlin Heidelberg 2005.