Approximate Computing Based Adder Design for DWT Application

Abstract

Approximate computing is gaining popularity in hardware design of different application circuits. The bit-width reduction in approximate computing reduces the power requirement and chip area though it introduces error in the processed output. In this paper, we have proposed approximate computing based various designs of approximation of mirror adder (MA) circuit, which can be used to implement discrete wavelet transform (DWT) hardware for various image processing applications. We have also used voltage-scaling approach in our design, which reduces the power requirement appreciably. We have studied four levels of approximation of mirror adder and among them the fourth level of approximation is tested and justified for the design application. The goodness of our design is well justified as it shows marginal reduction in signal to noise ratio with a good reduction of layout area and power. We have used 180 nm technology node in our proposed ASIC design.