Implementation of power efficient flash analogue-to-digital converter

Citations of this article
Mendeley users who have this article in their library.


An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC) is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder.The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL) to maintain high speed and low power dissipation.The proposed 5-bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V.The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL) value of -0.30 LSB and differential nonlinearity (DNL) value of -0.24 LSB, of the flash ADC.




Lakshmi, T. S., Srinivasulu, A., & Shaker, P. C. (2014). Implementation of power efficient flash analogue-to-digital converter. Active and Passive Electronic Components, 2014.

Register to see more suggestions

Mendeley helps you to discover research relevant for your work.

Already have an account?

Save time finding and organizing research with Mendeley

Sign up for free