An exact zero skew clock routing algorithm using the Elmore delay model is presented. Recursively in a bottom-up fashion, two zero-skewed subtrees are merged into a new tree with zero skew. The algorithm can be applied to single-staged clock trees, multi-staged clock trees, and multi-chip system clock trees. It is ideal for hierarchical methods of constructing large systems. All subsystems can be constructed in parallel and independently, and then interconnected with exact zero skew. Experimental results are presented.
CITATION STYLE
Tsay, R. S. (1992). Exact zero skew. In 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers (pp. 336–339). Publ by IEEE. https://doi.org/10.1007/978-1-4615-0292-0_40
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