3D charge trap NAND flash memories

Abstract

This chapter starts off with 2 vertical channel architectures named BiCS (Bit Cost Scalable) and P-BiCS (Pipe-Shaped BiCS), respectively. BiCS was proposed for the first time by Toshiba in 2007, and another version called P-BiCS was presented in 2009 to improve retention, source selector performances and source line resistance. Both options are based on a Charge Trap memory cell (Chapter 2). BiCS can definitely be considered as a major milestone in the history of 3D Flash. In the first 2 sections we dig into the details of BiCS and P-BiCS, while the second part of the chapter is devoted to the evolutionary path of V-NAND, which is the first 3D architecture that reached volume production.