FPGA Implementation of Recursive Algorithm of DCT

Abstract

Discrete cosine transformation (DCT) is one of an efficient tool which facilitates compression of speech and image signals. This paper focuses on FPGA implementation of discrete cosine transform (DCT-II) which is valid for, where N is the length of input sequence and. The architecture used is recursive in nature and implemented with reduced hardware complexity. The structure is designed using Verilog Hardware Description Language (HDL) and Zybo Zynq-7000 Development FPGA board is used for implementation. The design utilized LUTs, IOB, DSPs, and Flip flops and takes 26 clock cycles to compute all the output coefficients of DCT.