Probing semiconductor technology and devices with scanning spreading resistance microscopy

Abstract

As the downscaling in semiconductor industry continues, the correct operation of devices becomes critically dependent on the precise location and activation of the dopants in two dimensions. For Si technology, Duane had already determined in 1996 that, in the 0.25-μm CMOS technology, a 10-nm decrease in the channel length was responsible for a more than 10% increase in the gate-to-drain overlap capacitance [1]. In the 65-nm devices processed today, effects of shifts in lateral position of a few nanometers or of variations in concentration of a few percent in the channel are drastically more pronounced. © 2007 Springer Science+Business Media, LLC.