Comprehensively exploring the design space

Abstract

Design space exploration (DSE) is an iterative procedure to walk through the space of possible designs and find an optimal solution according to some well-defined objectives. The DSE problem is considered to be two orthogonal issues: How can a single design point be evaluated? How can the design space be covered during the exploration process? The latter question arises since an exhaustive exploration of the design space by evaluating every possible design point is usually prohibitive due to the sheer size of the design space. The chapter gives a comprehensive overview of existing methods for DSE. This can be classified into methods for evaluating, covering, and pruning the design space. The established Y-chart scheme (Fig. 5.1) serves as a basis for illustrating DSE techniques. The Y-chart implements the separation-of-concerns principle by keeping specifications of the application (benchmark) and architecture clearly separated. A systematic mapping between the two aspects can then drive an automated exploration of the design space. Trade-offs between cost functions and optimization strategies are revealed. We continue with a description of the Tipi architecture development system in this context. Tipi prefers a guided search of the design space for ASIPs, where the designer starts from an initial design and refines the architecture iteratively. By offering the generation of RT-level verilog®, multi-objective search can be supported, e.g. in terms of execution time and silicon area. The memory subsystem of a programmable platform can be explored independently of the computation part. The design space is pruned by analytical models and the set of remaining designs is explored exhaustively. We also propose a method for adaptively choosing exploration algorithms according to constraints on evaluation resources, such as the maximum execution time. In the following section we introduce some basic terminology and illustrate why DSE is a hard optimization problem. In Section 2, we compare singleobjective with multi-objective optimization in general. Section 3 lists common objectives and cost functions. Section 4 reviews methods used for evaluating the quality of a single design point, whereas Section 5 surveys methods for walking through the design space. This discussion also includes methods for pruning the design space. Section 6 finally shows, how the design space for ASIPs and memory subsystems can be explored comprehensively in our Tipi design framework. © 2005 Springer Science+Business Media, Inc.