Implementation of capacitor multiplier with cell-based variable transconductance amplifier

Abstract

Portable and implantable devices dictate the system integration and low power consumption. Digital integrated circuits (ICs) design with small-size transistors enables system integration and low power consumption. However, analogue IC design for biomedical application is critical for system integration and low power consumption. The presence of passive circuit elements such as capacitors that occupies more area on the chip has led the analogue IC's designers to the search for different solutions. Capacitor multiplier is one of intelligent solution for system integration of analogue processing unit of biomedical applications. In this work, a new capacitor multiplier circuit is proposed with recently recommended cell-based variable transconductance amplifier. The performance of the proposed circuit is verified with post-layout simulations and worst-case analysis under 135 corners including variations of process, temperature and power supply. The multiplication factor of the designed capacitor multiplier is 98. The verification of the designed circuit is proved in Cadence environment with TSMC 0.18 μm technology.