Fault loop impedance measurement in low voltage network with residual current devices

Abstract

In every low voltage electrical installation initial verification and periodic verification shall be performed. One of the test performed during the verification is fault loop impedance measurement. This measurement enables to verify effectiveness of automatic disconnection of supply which is the most often used means of protection in case of fault. Residual current devices - obligatory in particular circuits - cause the problem in fault loop impedance measurement. They trip out during the measurement and proper verification of the installation is impossible. Detailed analysis of the meters and residual current devices tripping circuits enables to find solution for proper performance of the measurement. The paper concerns the sources of the unwanted tripping of residual current devices during fault loop impedance measurement and indicates solutions for convenient measurement.