A 10-bit successive approximation analog-to-digital converter

Abstract

A 10-bit successive approximation analog-to-digital converter is presented. All circuits necessary for the operation of the converter are designed in a 0.18μm CMOS technology. In the logical part of the converter special attention is paid to the design of single clock flip-flop. A R-2R network architecture is used in digital-to-analog converter implementation. A comparator with rail-to-rail common mode range is used to provide the conversion of the analog voltage ranging from 0 to the supply voltage. The converter is designed for 1.8V power supply, the total power consumption of the converter is about 500 μW, and the resolution of 10 bits is achieved at 2MSamples/s.