Compiling applications for ConCISe: An example of automatic HW/SW partitioning and synthesis

Abstract

In the ConCISe project, an embedded programmable processor is augmented with a Reconfigurable Functional Unit (RFU) based on Field- Programmable Logic (FPL), in a technique that aims at being cost-effective for high volume production. The target domain is embedded encryption. In this paper, we focus on ConCISe’s programming tool-set. A smart assembler, capable of automatically performing HW/SW partitioning and HW synthesis, generates the custom operations that are implemented in the RFU. Benchmarks carried out with ConCISe’s simulators show that the RFU may speed up offthe- shelf encryption applications by as much as 50%, for a modest investment in silicon, and with no changes in the traditional application programming flow.