Energy-efficient 64-bit asynchrobatic adder

Abstract

A 64-bit Carry Look-ahead Adder (CLA) with radix-four structure is implemented using CMOS and FinFET-based asynchrobatic logic. The performance of designed adder circuits is assessed by comparing their power, energy, and power-delay product with those using 45 nm static CMOS technology over a range of frequencies and supply voltages. The results obtained reveal power and energy savings of up to 82 and 97% for CMOS and FinFET asynchrobatic adders, respectively, as compared to static CMOS circuits. A maximum PDP improvement of 89.47% at 0.5 V supply voltage is obtained with FinFET technology.