Single fully differential second generation current conveyor based four-quadrant analog multiplier design and its applications

Abstract

This manuscript presents a new fourquadrant analog multiplier using a recently reported current mode active building block, namely the Fully differential second generation current conveyor (FDCCII). The proposed circuit employs single FDCCII and two NMOSFETs only, thus has simple architecture. It is fully-integrable as no other external passive component has been used. Non-ideal behaviour of the reported configuration has been analysed considering current and voltage tracking errors of the FDCCII. Workability of the derived multiplier is verified with PSPICE (Cadence 16.6) simulations using model parameter of TSMC 0:35μm CMOS process and found to be in close agreement with theoretical anticipations. The static power consumption of the circuit is 0.107mW. The circuit works well with good linearity (nonlinearity error ≤ 0:96%) for the input voltage range of ±0.5V for a supply voltage of ±1V and the output is insensitive to temperature variation. Simulation results show that the -3dB bandwidth of the proposed multiplier is 20.67MHz and the output referred noise is less than 9nV/√Hz at 1kΩ load condition. Monte- Carlo analysis has also been performed for the proposed configuration. The applicability of the reported multiplier as amplitude modulator, squarer, and frequency doubler are also demonstrated.