Test of power management structures

Abstract

Shrinking technology nodes offer higher levels of integration and better performance. However, they are accompanied by increased dynamic (switching) and static (leakage) power densities. As seen in previous chapters, a wide array of power management technologies is used to control dynamic and static power in integrated circuits. Those include clock gating and various types of power gating techniques. Power gating and multiple voltage supplies usually result in the use of special low-power cells such as state-retention registers, isolation cells, and level shifters. In addition to the challenges inherent in testing logic that can operate in multiple power modes, it is necessary to thoroughly test all the power management features including the clock gaters, power gaters (or switches), the logic that controls them, and the aforementioned low-power cells. Testing this logic will be presented in this chapter, as well as a method for validating the integrity of the power distribution networks. © 2010 Springer-Verlag US.